The present invention relates to a semiconductor device having a packaged structure, and a method of producing the semiconductor device. In particular, the present invention relates to a semiconductor device called a Wafer level Chip Size Package (referred to as W-CSP).
Recently, it has been required to reduce a size and a thickness of a semiconductor device. To this end, there has been developed a semiconductor device called a wafer level Chip Size Package (W-CSP), in which an outer size of a package is substantially same as that of a semiconductor chip.
Patent Reference 1 has disclosed a semiconductor device of this type (W-CSP), in which it is possible to reduce a stress generated in an outer terminal and a boundary between the outer terminal and a re-distribution wiring pattern, thereby improving reliability of the semiconductor device.
Patent Reference 2 has disclosed a method of producing a semiconductor device of this type (W-CSP). In the method, when a pots electrode is formed, the post electrode is plated under a plating condition different from that in plating a wiring pattern. Accordingly, it is possible to reduce a stress generated due to a difference in thermal expansion coefficients between a semiconductor substrate of W-CSP and a mounting board.
Patent Reference 1: Japanese Patent Publication No. 2004-6486
Patent Reference 1: Japanese Patent Publication No. 2005-64473
In general, after a W-CSP is mounted on a mounting board, the W-CSP functions as a semiconductor device. When or after the W-CSP having a post electrode is mounted on the mounting board, an external stress applied to the W-CSP is concentrated on an outer terminal, the post electrode, and a post electrode mounting portion, i.e., a part of a re-distribution wiring pattern. The post electrode is also called a column electrode or a protrusion electrode. When such an external stress is applied, a wiring pattern, i.e., a substantial element of the semiconductor device, situated below the re-distribution wiring pattern may be damaged. Further, a crack may be generated in an interlayer insulation layer, thereby deteriorating substantial electrical property of the semiconductor device.
In view of the problems described above, an object of the present invention is to provide a semiconductor device to solve the problems of the conventional semiconductor device. In particular, it is possible to prevent a substantial element such as a wiring pattern from being damaged when an external stress is applied upon or after mounting the semiconductor device or W-CSP on a mounting board. Accordingly, it is possible to prevent substantial electrical property of the semiconductor device from deteriorating.
Further objects and advantages of the invention will be apparent from the following description of the invention.